1. Field of the Invention
This invention relates to the field of power management and power management apparatus, in particular power management integrated circuits, for supplying and regulating power to electrical devices, in particular to portable electrical devices.
2. Description of the Related Art
Many electrical devices include some sort of power management functionality. A power management unit, which is typically a power management integrated circuit (PMIC), is typically arranged to receive power from a power supply, which may be one of a plurality of possible power supplies, and provide appropriately controlled and regulated power to one or more power domains within the device in response to the power requirements thereof. As used in this specification the term “device” is used to refer to an electrical product, for example a mobile telephone, media player or personal computer and the like.
The power requirements of such electrical devices may vary depending on the usage of the device and also any power settings applied to a device in a particular mode of operation. For example consider an electrical device having a processor such as a CPU. A high clock speed may be required during periods when there is a lot of processing to be performed, for instance when performing processor intensive tasks. However when performing tasks which are not so processor intensive a lower clock frequency may still give acceptable performance and such a lower frequency would offer direct power savings. The voltage supplied to the processor can often be reduced at lower clock frequencies.
To conserve power the processor may therefore be arranged to vary its clocking frequency in accordance with its loading and the power management unit may be arranged to vary the supply voltage supplied to the processor accordingly.
Electrical devices may also be arranged to have a number of different operational states with the functionality of the device being different in each operational state. For example an electrical device may be arranged to have a device On state, where the device is functioning and a device Off state where the device main functionality of the device is off or dormant. The device may also have a sleep or stand-by device state which is a low power state.
To provide for the various device operational states the PMIC is therefore arranged to provide a plurality of PMIC power states. There may not be a one-to-one correspondence between PMIC power states and device operational states. There may for instance be many device On states involving enabling and disabling various circuit blocks within a common power domain which would be indistinguishable in terms of PMIC configuration, so would all map to a single PMIC ON state. To avoid confusion herein, PMIC power states are denoted by block capitals, device operational states are not.
The PMIC may provide a PMIC ON state where power is supplied to the majority of the device sub-systems. The PMIC may also provide one or more PMIC SLEEP states where several device functions may be unpowered or operating at much reduced power levels but some device sub-systems such as device memory or communication modules for example remain powered. In a PMIC OFF state the majority of device functions may be unpowered but, in some devices, there may be various functions, such as a real time clock for example, which remain powered by an internal battery.
Some PMICs may provide more than one ON state or different types of SLEEP state which can allow a device to have different functionality. SLEEP states are sometimes referred to as STAND-BY or HIBERNATE states. The term “SLEEP state” will be used throughout this specification as a non-limiting example of a power state of a PMIC and will be taken to include STAND-BY and HIBERNATE power states. The skilled person will appreciate however that what a system architect might designate as a PMIC SLEEP state may, in some devices provide greater functionality than what is designated as an ON state.
Various device functions, i.e. device sub-systems, that are separately powered may form separate power domains within the device. Power domains may also exist where different sub-systems within the device operate at different voltages. A power domain therefore comprises one or more device sub-systems which receive a common power supply. Different power domains may be powered independently of one another and/or supplied with different voltages to one another. Different parts of a single chip may be implemented in different power domains. A single power domain may however comprise multiple chips within a device, or even parts of multiple chips.
The power management unit is therefore typically arranged with a plurality of power blocks, each power block being mapped and connected to a particular power domain to control and regulate the power supply thereto. As used herein the term “power block” refers to circuitry for providing an appropriate power supply to an individual power domain, i.e. to circuitry for controllably supplying power to a load (the relevant power domain) using the supplies available to the PMIC. The power blocks, which typically comprise some sort of voltage regulator (e.g. a linear regulator, a switch-mode converter using an inductance or a charge pump or any combination thereof) or power switch, are typically arranged with various configuration settings that allow parametric control of the power blocks. For example the output voltage configuration may be controlled.
Power state transitions, i.e. a transition from one power state of the power management unit, e.g. ON, SLEEP or OFF, to another different state, may be initiated in various ways. For instance a main control button operable by the user could be used to initiate a power state transition of the power management unit, for instance from SLEEP to ON or vice versa. Similarly a user initiated power state transition of the power management unit could be triggered through receipt of a command through an appropriate communications interface of the device, e.g. an infrared or RF receiver, which is then transmitted over a suitable command and control bus to the power management unit. A user initiated power state transition of the power management unit could be triggered through receipt of a command from a touch screen interface or accelerometer in the device.
The operating system of the device itself may also be arranged to initiate a transition of power state of the power management unit based on activity of the device. For instance a device which is not performing any user initiated tasks may, for example, instruct the power management unit to transition from the ON state to the SLEEP state after a certain period of inactivity. A device with a power management unit in a SLEEP state may initiate transition of the power management unit to an ON state if some active monitoring circuitry detects some activity, e.g. receipt of some incoming data or a user using a human machine interface such as a keypad or the like. For instance a mobile telephone in a device stand-by state in which the power management unit is in a low power SLEEP state may be arranged to be able to detect an incoming call to be able to wake up if an incoming call is detected. In this example the RF receiver will remain powered by the power management unit in this SLEEP state.
A power state transition may also be initiated by the power management unit itself. For example, where the only available power supply is an internal battery, a power state transition to the OFF power state may be initiated if the battery level drops below a certain threshold.
In a power state transition at least one power domain of the device may typically transition from being active to being inactive or vice versa. For example in response to a shut down command the power management unit may stop supplying power to all sub-systems of a device apart from sub-systems for detecting a start up command (e.g. a power button arrangement and/or an infrared or RF receiver) and possibly a real time clock system. On a subsequent start up command the power management unit may supply power to all device sub-systems again.
In some devices it is beneficial to shut various device sub-systems down in a predetermined order. At least some of the power domains of the device may be connected to one another, possible via level shifting circuitry. Depending on the various circuits forming the power domains there may be a need to power some domains before others in a device start-up procedure and/or remove power from some power domains before others in a shut-down process to avoid any problems with analogue latch-up or back-powering of domains resulting in corruption of device operation or damage to the device.
Power management units may therefore be provided with a sequencer for activating and deactivating the power blocks which supply the various power domains within the device in a predetermined sequence. The required sequence is stored in memory that is readable by the power management unit. A power state transition, triggered by a power state transition command, may therefore involve controlling the appropriate power blocks to power and/or depower, i.e. to remove power from or to power down, different power domains within the device in the predetermined sequence.
One possible problem in applying power state transitions is that, for some electrical devices, the operating system of the device may be running various processes at the time that the power state transition command, i.e. a command for the power management unit to change from its present power state to a different power state, is issued. The power state transition command could be issued for a number of different reasons and, as mentioned above, could be issued at any time by a user hitting a power switch say or in response to a low battery detection by the power management unit. Thus an operating system of the device may not be in control over when a power state transition command is issued and may be performing a critical function when the command is issued.
For example some devices are arranged so that a device in an On state which is entering a low power state, (corresponding to the power management unit transitioning from an ON power state to a SLEEP power state), will store the current state of the operating system in a memory so the device can restore to the same state on transition back to the On state.
If the power management unit removes power to a critical part of the system, prior to successful termination of the critical processes or completion of a memory storing step this may lead to system instability, corruption or malfunction.
To address this problem various handshaking arrangements have been proposed. For instance one approach uses a separate hardware pin arrangement for communicating power state change requests between the operating system and the power management unit. The operating system only issues a power state transition command after most processes have been successfully terminated. However such handshaking arrangements typically require relatively complex hardware, which adds to the complexity and expense of the device, and may not be fully effective as the operating system needs to be active to some extent to perform the handshaking itself so not everything can be terminated.
To avoid corruption system architects often ensure that significant parts of the device remain powered in a power management unit SLEEP power state. This increases power consumption and reduces battery life compared to removing power from all non-functional device systems.